The biggest challenge the neuromorphic community faces today is to create

The biggest challenge the neuromorphic community faces today is to create systems that can be considered truly cognitive. On the other hand exploiting hardware dynamics to create adaptive systems rather than forcing the hardware to behave like mathematical equations seems to be a more strong methodology when it comes to developing actual hardware for real world applications. With this paper we make use of a novel time-staggered Winner Take All circuit that exploits the adaptation dynamics of floating gate transistors to model an adaptive cortical cell that demonstrates (genetic biases) and (environmental factors) play a crucial role in the formation of these feature maps. Different hardware and software methods have been explored to model self-organization. Each approach has a set of mechanisms that exploit the available techniques. While models built in software choose to use mathematical equations attempting to do the same in hardware can turn out to become extremely cumbersome (Kohonen 1993 2006 Martn-del-Bro and Blasco-Alberto 1995 Hikawa et al. 2007 On the other hand understanding the hardware dynamics and then building adaptive algorithms around it seems to be a more robust approach for building real world applications. To emulate activity dependent adaptation of synaptic contacts in electronic devices we look towards developing mind for inspiration. In the developing mind different axons linking to a RN486 post synaptic cell compete for the maintenance of their synapses. This competition results in synapse refinement leading to the loss of some synapses or synapse removal (Lichtman 2009 Misgeld RN486 2011 Turney and Lichtman 2012 Carrillo et al. 2013 Temporarily correlated activity helps prevent this competition whereas uncorrelated activity seems to enhance it (Wyatt and Balice-Gordon 2003 Personius et al. 2007 Moreover exact spike timing takes on a key part in this process e.g. when activity at two synapses is definitely separated by 20 ms or less the activity is definitely perceived as synchronous and the removal is prevented (Favero et al. 2012 Apart from the biological relevance synapse removal as a means of honing neural contacts is also suitable for implementation in large level VLSI networks because in analog hardware it is hard to create Rabbit Polyclonal to ADORA2A. fresh connections but it is achievable to stop using some contacts. Although some digital methods work around this by using virtual contacts using the Address Event Representation however in purely analog designs for ease of management of large scale contacts synapse removal is best suited. In order to implement synapse pruning we need to have nonvolatile flexible synapses which are best displayed by floating gate synapse or memresistors (Zamarre?o-Ramos et al. 2011 While memresistor technology is still in development floating gate transistors have gained widespread acceptance because of the capacity to maintain charge for very long periods and the simplicity and accuracy with which they can be programmed during operation (Srinivasan et al. 2005 Floating gate remembrances are being used for numerous applications like pattern classification (Chakrabartty and Cauwenberghs 2007 sensor data logging (Chenling and Chakrabartty 2012 reducing mismatch (Shuo and Basu 2011 etc. They have also found extensive software in neuromorphic systems (Diorio et al. 1996 RN486 Hsu et al. 2002 Markan et al. 2013 We consequently extend the study of adaptive behavior of floating gate pFETs and demonstrate how this adaptive competitive and cooperative behavior can be used to design neuromorphic hardware that exhibits orientation selectivity a widely studied phenomenon observed in the visual cortex. Prior attempts toward hardware realization of orientation selectivity can be classified into RN486 two groups (1) Snow Cube models (2) Plastic models. Ice cube models e.g. the model by Choi et al. (2005) assumes prewired feed-forward and lateral contacts. Another related model by Shi et al. (2006) uses DSP and FPGA chips to build a multichip modular architecture. They use Gabor filters to implement orientation selectivity. This approach provides an superb platform for experimentation with.